1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory for storing data by trapping charges in a plurality of dielectric films, and an operation method thereof.
2. Description of the Related Art
A nonvolatile semiconductor memory is a semiconductor memory having nonvolatile property, highly integrating property and an electric rewriting function. In a so called Erasable and Electrically Programmable Read Only Memory (EEPROM), a Floating Gate (FG) type wherein a conductor called a floating gate is provided on a gate insulation film in a state of being completely surrounded by oxide films, etc. to be electrically insulated and charges are stored in the floating gate, a Metal-Oxide-Nitride-Oxide-Semiconductor (MONOS) type and a Metal-Nitride-Oxide-Semiconductor (MNOS) type wherein a charge storing film obtained by stacking a plurality of dielectric films is provided and data is stored by controlling a charge amount to be stored in charge traps in the charge storing film are known.
As a method of injecting the charges to the charge storing film, other than using a tunneling phenomenon of charges in a dielectric film, there is a method of energetically exciting charges to an extent of becoming capable of getting over an insulation barrier of a lowermost layer of the dielectric films, such as so called Cannel Hot Electron (CHE) injection (for example, refer to “Electron Device Letter (EDL)” EDL-21, 2000, p.543 written by Boaz Eitan, issued by the Institute of Electrical and Electronics Engineers (IEEE)).
In a nonvolatile memory described in the quoted article, by using as a reference a potential of an N-type impurity diffusion region (for example, 0V) contacting one over a P-type semiconductor region wherein a channel is formed by an N-type inversion layer with minority carriers, a writing drain voltage of, for example, 4 to 5V is applied to the other N-type impurity diffusion region, and in that state, a writing pulse (writing gate voltage) of, for example, 10V or so is applied to the gate electrode. As a result, electrons are supplied into the channel from one impurity diffusion region being applied 0V to serve as a source and accelerated in the channel, so that hot electrons are generated at the channel end of the drain side. The hot electrons are injected from the channel end of the drain side to the charge storing film (ONO film).
When reading data, roles of the source and the drain are reversed from those in the above writing, a reading drain voltage (for example, 1.5V) is applied between the two impurity diffusion regions and a reading gate voltage (for example, 3.0V) is applied to the gate electrode. During writing, a threshold voltage of a memory cell transistor varies in accordance with a charge storage amount on the source side. Thus, a memory transistor turns on or off in accordance with the charge storage amount on the source side under the condition that a voltage at the time of the above reading is applied, and the information is detected by a sense amplifier, etc. This reading method is called a reverse read method because the electric field direction of the source and the drain is reversed from those at the time of writing. In the above quoted article, two-bit data is stored in one cell by injecting several hundreds of electrons respectively to both ends of the charge storing film, and two-bit data is read by the reverse read performed twice by reversing the source and the drain.
When erasing data, a positive voltage is applied to an impurity diffusion region on the side in which electrons desired to be erased are stored and a negative voltage is applied to the gate, so that hot holes are generated by band-to-band tunneling on the impurity diffusion region side and the hot holes are injected to a part of the charge storing film storing the electrons to be erased so as to erase the data. In the above quoted article, two-bit data is erased by performing this operation twice by switching the impurity diffusion region to be applied with the positive voltage.
There are problems below in a nonvolatile memory apparatus described in the quoted article.
First, while a MONOS type memory transistor of the related art was capable of using a lower voltage than that in the FG type, an efficiency of CHE injection of electrons at the time of writing data was poor and the voltage was not low enough, that is, a voltage of nearly 10V was necessary. Therefore, a transistor having a high breakdown voltage was required in a peripheral circuit of the memory, so that the production process became complicated and a reduction of the production cost became difficult. Also, delay of a pulse and a power consumption were large and usage of the nonvolatile memory apparatus was limited.
Secondary, it is also possible to lower the voltage by improving the CHE injection efficiency by optimizing the ONO film and the impurity regions, however, in that case, read disturbance at the time of a reading operation becomes notable because writing is a low voltage operation. That is, at the time of reading a change of a threshold voltage in accordance with a storing charge amount on the source side when reading data, in the case where a writing voltage is made low, weak writing is liable to be caused by an electric field imposed on the end portions of the charge storing film on the drain side. Thus, while repeating the reading for many times, there is a disadvantage that an unignorable amount of electrons are forcibly injected on the drain side and data is destroyed in the worst case.
Thirdly, there are disadvantages on erasing as below.
In an erasing operation of electrically canceling by injecting hot holes charges written in a part of the end of the drain side by the CHE injection, when the erasure is not sufficient, a threshold voltage of the memory transistor becomes that of the written region. While, when the erasure is sufficiently done, excessive erasure is caused, that is, the threshold of the erased region becomes lower than that of an initial channel-forming region wherein no writing is performed. When the excessive erasure is caused, the threshold voltage of the memory cell transistor is mostly determined by that of the channel-forming region.
The threshold voltage of the channel-forming region is adjusted by ion implantation on the initial stage of the process, but it is liable to vary in a memory cell array or between wafers because the concentration is relatively low in the ion implantation at this time and the threshold voltage is easily changed due to thermal transition of processes after that. When determining an erasure condition by aiming a threshold voltage level on the boundary of causing the excessive erasure and attempting sufficient erasure as much as possible, the excessive erasure is always caused in a part of the memory cell transistor and the threshold voltage of the memory transistor tends to vary thereby.
On the other hand, when erasure is not done much so as not to even partially cause the excessive erasure, the threshold voltage at a low level of the memory cell in this case becomes that of a data written region. However, the threshold in the middle of erasure when the erasure is not completely done is sensible to changes of an erasure time and easily affected by pulse delay, so that it tends to largely vary. Furthermore, in this case, a threshold voltage difference between writing and erasing is not secured much, so an operation at a low voltage becomes difficult.
Namely, in the memory cell structure of the related art, the threshold voltage at erasure largely varies regardless of controlling of an erasure time at the last analysis.
The third disadvantage is expected to be furthermore important as a significant matter in pursuing a lower voltage in the future. When pursuing a lower voltage in this way, eventually, complicated control of unifying an erasure level for every bit, etc. will be required and it may result in a state of not being capable of shortening a data rewriting time or causing a longer data rewriting time.